Company:
Qualcomm Semiconductor Limited
Job Area:
Engineering Services Group, Engineering Services Group > Mask Layout Design
General Summary:
Layout Engineer to design, implement and verify process test circuits and test structures in sub-5nm process nodes to enable process team device characterization, electrical target definition and validation foundry SPICE modesl. Test circuits including ring oscillators, SRAM and matching transistor mux-able circuits. Test structures include basic transistors in various local layout dependent configurations.
Minimum Qualifications:
• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
High School diploma or equivalent and 8+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
• 4+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).
Must have tool experience using:
1) Cadence design suite of tools 5.1.4*, 6.1.*, ic12 (layout+schematic)
2) Calibre verification suite (DRC, LVS, ERC, LPE, Softcheck)
3) Design Management tools using Synchronicity's DesignSync
4) UNIX and script automation
3+ years minimum layout design experience in sub-5nm CMOS commercial technologies
Must have relevant test structure design, implementation, verification, assembly and tapeout experience on product testlines. Test structures include, but not limited to, resistors, capacitors, MOSFETs, ring oscillators, matched circuits.
Able to capture, design, develop and implement process technology test structures and circuits that allow easy re-use, with consistency across various layout styles that allow flexible updates with minimal effort.
Ensure layout compliance to Design-Of-Experiment (DOE) documentation and intent. Work with process team device and module owners to translate DOE documentation to functional error-free layouts with minimal supervision.
Knowledgeable in layout dependent and parasitic effects. Multi-patterning, finfet technology familiarity required.
Independently perform dataprep operations like dummy fill, multi-pattern coloring.
Independently debug Calibre verification results with corrections either to layout or schematic in a timely fashion.
Applicants: If you need an accommodation, during the application/hiring process, you may request an accommodation by sending email toaccommodationsupport
Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm’s toll-free number found herefor assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.
Qualcomm is an equal opportunity employer and supports workforce diversity.
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