At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position Description:
•Skillful capable of AMS layout Design area: Matching guides, Resistor/capacitor placement, reduce coupling&noise, senstive signals routing, etc.
•Skillful experience in Analog IC top level chip assembly including floorplanning and block layout
•Skillful experience in high speed projects like: DDR, GDDR, Serdes, etc; experience in IP layout is a plus
•Experience in layout project management and delivery work is a plus
•Ability to coordinate with analog IC circuit team to ensure robust, efficient, consistent and successful delivery of analog IC layout.
•Experience in communcation with project manager and digital P&R team is a plus
•Proficient with Cadence layout/verify tools like Virtuoso XL, Pegasus/PVS; Mentor Calibre, etc..
•Proficient with EMIR tool like Voltus-fi is a plus
•Hands-on experience conducting DRC/LVS/ERC analysis, EMIR analysis, and recommending appropriate solutions
•Experience in PERC run is a plus
•Fundamental understanding of IC design technology and process/methodology; Knowing about finfet is a plus
•Experience in ESD/Latch-up is a plus.
•Good English speaking/listen is requied.
Position Requirements:
BSEE degree with 6+ years of applicable experience in analog layout.
Essential that the individual demonstrates strong communication, verbal and written, and project management skills.
Requires good communication skills in English and Chinese.
•Skillful capable of AMS layout Design area: Matching sense from transistor, Resistor and capacitor, Power and Ground coupling, Signal path from Differential pairs, etc.
•Proficient with Cadence layout tools specifically Virtuoso XL and Assura (Cadence 6.1 experience a plus)
•Ability to coordinate with the other analog IC circuit layout, ensuring robust, efficient, consistent and successful delivery of analog IC circuit layout.
•Fundamental understanding of IC design technology and process/methodology
•Skilled in Analog IC top level chip assembly including floorplanning and block layout
•Hands-on experience conducting DRC/LVS analysis and recommending appropriate solutions
Position Requirements:
BSEE degree with 1-2 years of applicable experience in analog design industry.
Essential that the individual demonstrates strong communication, verbal and written, and project management skills.
Requires good communication skills in English and Chinese.
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